Method for manufacturing a semiconductor device

ABSTRACT

The present invention makes it possible to increase the selectivity of a gate insulation film in an active element formed in a wiring layer. A semiconductor device according to the present invention has a bottom gate type transistor using an antireflection film formed over an Al wire in a wiring layer as a gate wire.

BACKGROUND

The present invention relates to a semiconductor device, in particularto a layout structure of a bottom gate type MIS (Metal InsulatorSemiconductor) formed in a wiring layer.

A technology of forming an active element having switch function andrectification function in a wiring layer is known like a semiconductordevice described in Japanese Unexamined Patent Publication No.2010-141230 (refer to Patent Literature 1). By forming an active elementin a wiring layer, it is possible to change the function of a wholesemiconductor device significantly without changing the layout of asemiconductor element formed over a semiconductor substrate.

FIG. 1 is a view showing an example of the structure of a semiconductordevice described in Patent Literature 1. In FIG. 1, a semiconductordevice described in Patent Literature 1 has a wiring layer 900 and asemiconductor element 910 formed over a semiconductor substrate. Thewiring layer 900 has an insulation film 921 formed over a diffusionprevention film 901 and a wire 904 and a via 903 embedded in theinsulation film 921. A barrier metal not shown in the figure is formedat an interface between the wire 904 and the via 903 and otherstructures (the insulation film 921, the diffusion prevention film 901,and the wire 904). A diffusion prevention film 911 is formed over thewiring layer 900 and an insulation film 922 and a wire 916 and a via 915embedded in the insulation film 922 are formed over the diffusionprevention film 911. The semiconductor element 910 has a gate electrode902, a gate insulation film 911, and a semiconductor layer 912. Thesemiconductor layer 912 is formed over the gate insulation film 911 andcoupled to a wire 914 through a via 913. The gate electrode 902 isformed under the gate insulation film 911 in the wiring layer 900. Abarrier metal not shown in the figure is formed at an interface betweenthe wire 914 and the via 913 and other structures (the insulation film922 and the semiconductor layer 912).

PREVIOUS TECHNICAL LITERATURE Patent Literature

[Patent Literature 1]

Japanese Unexamined Patent Publication No. 2010-141230

SUMMARY

Cu has a high diffusion coefficient and is likely to diffuse in aninterlayer insulation film and hence, when a Cu wiring process is used,it is necessary to form a barrier metal and a diffusion prevention film(also called a wiring cap insulation film) between wiring layers. In asemiconductor device described in Patent Literature 1, a bottom gatetype transistor (also called a back gate type transistor or an invertedtype transistor) using a Cu wire as a gate wiring 902 is materialized byusing a diffusion prevention film formed over a wiring layer 900 as agate insulation film 911.

In a Cu wiring process however, it is necessary to form a barrier metaland a diffusion prevention film capable of preventing the diffusion ofCu as stated above. For the reason, when an active element is formed ina wiring layer by using a Cu wiring process, it is concerned that amaterial constituting a gate insulation film is limited to a diffusionprevention film capable of preventing the diffusion of Cu. Consequently,it is desired to increase the selectivity of a material usable as a gateinsulation film of a bottom gate type transistor formed in a wiringlayer.

A semiconductor device according to the present embodiment has a bottomgate type transistor that uses an antireflection film formed over an Alwire in a wiring layer as a gate wire.

The present invention makes it possible to increase the selectivity of agate insulation film in an active element formed in a wiring layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view showing the configuration of a semiconductor devicedescribed in Japanese Unexamined Patent Publication No. 2010-141230.

FIG. 2 is a view showing an example of the configuration of asemiconductor device according to First Embodiment.

FIG. 3 is a view showing another example of the configuration of asemiconductor device according to First Embodiment.

FIG. 4A is a view showing an example of a method for manufacturing asemiconductor device shown in FIG. 2 or 3.

FIG. 4B is a view showing an example of a method for manufacturing asemiconductor device shown in FIG. 2 or 3.

FIG. 4C is a view showing an example of a method for manufacturing asemiconductor device shown in FIG. 2 or 3.

FIG. 4D is a view showing an example of a method for manufacturing asemiconductor device shown in FIG. 2 or 3.

FIG. 4E is a view showing an example of a method for manufacturing asemiconductor device shown in FIG. 2 or 3.

FIG. 5 is a view showing an example of the configuration of asemiconductor device according to Second Embodiment.

FIG. 6A is a view showing an example of a method for manufacturing asemiconductor device shown in FIG. 5.

FIG. 6B is a view showing an example of a method for manufacturing asemiconductor device shown in FIG. 5.

FIG. 6C is a view showing an example of a method for manufacturing asemiconductor device shown in FIG. 5.

FIG. 7 is a view showing the planar structure of a bottom gate typetransistor according to an embodiment.

FIG. 8 is a view showing the cross-sectional structure taken on lineA-A′ of a bottom gate type transistor shown in FIG. 7.

FIG. 9 is a view showing an example of the structure(high-voltage-resistant structure) of a bottom gate type transistoraccording to an embodiment.

FIG. 10 is a view showing an example of the relation of connectionbetween a wiring layer active element and an underlying logic circuit(Logic circuit formed on the semiconductor substrate) according to anembodiment.

FIG. 11 is a view showing another example of the relation of connectionbetween a wiring layer active element and an underlying logic circuitaccording to an embodiment.

FIG. 12 is a view showing still another example of the relation ofconnection between a wiring layer active element and an underlying logiccircuit according to an embodiment.

FIG. 13 is a view showing an example of the configuration of asemiconductor device consolidating a wiring layer formed through an Alwiring process and a wiring layer formed through a Cu wiring process.

DETAILED DESCRIPTION

Embodiments according to the present invention are hereunder explainedin reference to attached drawings. In the drawings, identical or similarreference symbols represent identical, similar, or equivalentcomponents.

1. First Embodiment

The configuration of a semiconductor device 10 according to FirstEmbodiment of the present invention is explained in detail in referenceto FIGS. 2 and 3. FIG. 2 is a view showing an example of theconfiguration of a semiconductor device according to First Embodiment.In FIG. 2, a semiconductor device 10 according to First Embodiment hasan underlying logic element 20 formed over a substrate 100, a pluralityof wiring layers 200, 300, 400, and 500, and a bottom gate typetransistor 11 (also called a wiring layer active element) formed in thewiring layer 400.

In the substrate 100 (preferably a monocrystal semiconductor substrate,for example an Si substrate), the underlying logic element 20 separatedinto parts by an element isolation layer 101 is formed. As an examplehere, a transistor having a gate wire 201, a source diffusion layer 102,and a drain diffusion layer 103 is shown as the underlying logic element20. Specifically, a diffusion region (the source diffusion layer 102 andthe drain diffusion layer 103) into which impurities (n-type impuritiesfor example) are injected is formed between the element isolation layer101 in the substrate 100 (a Psub substrate for example). The gate wire201 is formed in the upper layer at a channel region between the sourcediffusion layer 102 and the drain diffusion layer 103 through aninterlayer insulation film 220.

The first wiring layer 200 is formed over the underlying logic element20. The underlying logic element 20 is coupled to another element, apower source, or the like through the first wiring layer 200. Forexample, the first wiring layer 200 has a contact 210 coupling theunderlying logic element 20 to the second wiring layer 300 and a wirenot shown in the figure. The contact 210 includes a contact plug 203 anda barrier metal 202. For example, a W (tungsten) plug is preferably usedas the contact plug 203 and the barrier metal 202 exemplified by TiN isformed at the interface.

The second wiring layer 300 is formed over the first wiring layer 200.Each of the wiring layers 200, 300, 400, and 500 may have a structurecomprising a plurality of layers and here the second wiring layer 300comprises two interlayer insulation films 321 and 322. A wire 302 and avia 310 are formed in each of the interlayer insulation films 321 and322. Antireflection films 301 and 303 are formed over the top face andthe bottom face respectively at the interface between the wire 302 andeach of the interlayer insulation films 321 and 322. The antireflectionfilm 301 however may not be formed. The via 310 includes a via plug 305and a barrier metal 304. For example, a W (tungsten) plug is preferablyused as the via plug 305 and the barrier metal 304 exemplified by TiN isformed at the interface.

The third wiring layer 400 is formed over the second wiring layer 300.The third wiring layer 400 has a wire 402, a via 410, and the bottomgate type transistor 11 formed in an interlayer insulation film 420.Antireflection films 401 and 403 are formed over the top face and thebottom face respectively at the interface between the wire 402 and theinterlayer insulation film 420. The antireflection film 401 however maynot be formed. The via 410 includes a via plug 405 and a barrier metal404. For example, a W (tungsten) plug is preferably used as the via plug405 and the barrier metal 404 exemplified by TiN is formed at theinterface.

The bottom gate type transistor 11 has a wire 2, antireflection films 1and 3, a gate insulation film 4, and a semiconductor layer 5 and iscoupled to a wire 502 in the fourth wiring layer 500 through a barriermetal 7 and a contact plug 8. The wire 2 and the antireflection films 1and 3 comprise a material identical to the wire 402 and theantireflection films 401 and 403 in the third wiring layer 400. Theantireflection film 1 however may not be formed.

The wiring layers 200, 300, 400, and 500 in the present embodiment maypreferably be formed through an Al wiring process. That is, the wires 2,302, 402, and 502 comprise Al or a material containing Al. Further, amaterial having a power close to an Al wire (for example, TiN or alaminated material of TiN/Ti) is preferably used as the antireflectionfilms 3, 301, 303, 401, 403, 501, and 503. The gate insulation film 4,the semiconductor layer 5, and a hard mask insulation film 6 are stackedin sequence from the lower layer over the antireflection film 3. It ispossible to use an oxide film or a nitride film of various structures asthe gate insulation film 4 by using the antireflection film 3 as a gateelectrode. For example, the gate insulation film 4 may comprise aninsulation film containing any one of SiN, SiO₂, SiCN, SiON, SiCOH,Al₂O₃ (Al_(x)O_(y)), and Ta₂O₃ (Ta_(x)O_(y)). Otherwise the gateinsulation film 4 may contain a High-k material (for example, ZrO₂,HfO₂, La₂O₃, or LaAlO₃) having a high dielectric constant. Further, thegate insulation film 4 may comprise a stacked structure (for example,AlO₂/SiO₂, SiO₂/SiN, Al₂O₃/SiN, or Al₂O₃/SiO₂/SiN) formed by stackingthe above insulation film and the above High-k material. In the presentembodiment therefore, since the antireflection film 3 used in the Alwiring process is used as a gate wire, it is possible to select amaterial usable as the gate insulation film 4 without taking thediffusion of Al into consideration.

In a semiconductor device described in Patent Literature 1, since a Cuwire is used as a gate wire, a wiring cap insulation film for the Cuwire is used as a gate insulation film. In such a structure, it isnecessary to use a wiring cap insulation film (for example, SiN or SiCN)for preventing a Cu wire from diffusing as a gate insulation film andhence it is concerned that an applicable gate insulation film islimited. On the other hand, in a semiconductor device 10 according tothe present embodiment, it is not necessary to consider the diffusion ofa gate electrode and hence many materials can be used as the gateinsulation film 4. In the present embodiment therefore, in the casewhere transistor characteristics (Ion-Ioff characteristic (correlationbetween on-state current and off-state current), threshold voltagecharacteristics, etc.) and device reliability (BTI: Bias TemperatureInstability, hysteresis characteristics, etc.) deteriorate because ofthe gate insulation film 4, it is possible to improve thecharacteristics by changing the material and the laminated structure ofthe gate insulation film 4. That is, the present invention can make itpossible to improve the process margin of a bottom gate type activeelement formed in a wiring layer.

A channel region is formed at an inter-region (between a source regionand a drain region) to which a contact 9 is coupled in the semiconductorlayer 5. The region (the source region or the drain region not shown inthe figure) to which the contact 9 is coupled in the semiconductor layer5 is formed by introducing oxygen defects or impurities into thesemiconductor layer 5. An oxide semiconductor material is preferablyused for the semiconductor layer 5. Here, when the semiconductor layer 5functions as a P-type semiconductor layer, the semiconductor layer 5, asa P-channel material, includes any one of SnO, NiO, ZnO, Cu₂O, and NiOor may include a laminated structure of those. Meanwhile, when thesemiconductor layer 5 functions as an N-type semiconductor layer, thesemiconductor layer 5, as an N-channel material, includes any one ofInGaZnO, ZnO, InZnO, InHfZnO, those being materials of a ZnO system,SnO₂, and CuO or may include a laminated structure of those. Forexample, a laminated film comprising IGZO/Al₂O₃/IGZO/Al₂O₃ is preferablyused as the semiconductor layer 5.

The hard mask insulation film 6 used for processing the semiconductorlayer 5 and the gate insulation film 4 is formed over the semiconductorlayer 5. For example, SiN, SiO₂, SiCOH, or TiN is preferably used as thehard mask insulation film 6.

The contact 9 penetrating into the hard mask insulation film 6 at agiven location and reaching a wire (here, the antireflection film 501)formed in the fourth wiring layer 500 is formed over the semiconductorlayer 5. The contact 9 includes the contact plug 8 and the barrier metal7. For example, a W (tungsten) plug is preferably used as the contactplug 8 and the barrier metal 7 exemplified by TiN is formed at theinterface.

The fourth wiring layer 500 is formed over the third wiring layer 400. Asource and a drain (contact 9) of the bottom gate type transistor 11 arecoupled to another element, a power source, and the like through thefourth wiring layer 500. The fourth wiring layer 500 has the wire 502formed in an interlayer insulation film 520. The antireflection films501 and 503 are formed over the top face and the bottom face at theinterface between the wire 502 and the interlayer insulation film 520.The antireflection film 501 however may not be formed.

FIG. 3 is a view showing another example of the configuration of asemiconductor device according to First Embodiment. Whereas a contact 9of a W/TiN structure is used as a source contact and a drain contact ofa bottom gate type transistor 11 in the example shown in FIG. 2, a wirein a fourth wiring layer 500 is coupled to a semiconductor layer 5 byembedding a wiring material into a via hole in the example shown in FIG.3. The configuration of a semiconductor device 10 shown in FIG. 3 ishereunder explained on the parts different from the example shown inFIG. 2.

The structure of a semiconductor device 10 shown in FIG. 3 is the sameas the structure shown in FIG. 2 on the parts from a substrate 100 to asemiconductor layer 5 in a third wiring layer 400. In FIG. 3, anembedded wire 16 reaching a fourth wiring layer 500 through a givenregion in a hard mask insulation film 6 is formed over the semiconductorlayer 5. The embedded wire 16 shows a laminated structure comprising anantireflection film 13, a wire 14 (Al wire), and an antireflection film15 in sequence from the lower layer. The antireflection films 13 and 15show a laminated structure of TiN/Ti for example.

Successively, an example of a method for manufacturing a semiconductordevice 10 according to First Embodiment shown in FIG. 2 or 3 isexplained in reference to FIGS. 4A to 4E.

Firstly, an example of a method for manufacturing a semiconductor device10 shown in FIG. 2 is explained.

In FIG. 4A, an underlying logic element 20 formed in an Si substrate isformed through an ordinary semiconductor manufacturing process (forexample, forming a diffusion layer by injecting impurities into asubstrate 100 and forming a gate wire by masking and etching). Aninterlayer insulation film 220 is formed over the underlying logicelement 20, flattening treatment is applied by CMP (Chemical MechanicalPolishing) or the like, and wiring layers 200 and 300 are formed furtherthereover through an Al wiring process. An ordinary Al wiring processcan be used also for the wiring layers 200 and 300. For example, after afilm is formed with a laminated structure material by a sputteringmethod, a CVD (Chemical Vapor Deposition) method, a coating method, orthe like, a wire (antireflection film 301/wire 302/antireflection film303) of a laminated structure, a via 310, or a contact 210 is formedthrough patterning treatment by masking and etching. Here for example,an Al wire (TiN/Al/TiN), a via (W/TiN), or a contact (W/TiN) of alaminated structure is formed. Interlayer insulation films 220, 321, and322 (for example SiO₂) are formed over the formed wire, contact, andvia, flattening treatment is applied by CMP, and the wiring layers 200and 300 are formed.

In FIG. 4A, after a film of a laminated structure is formed with awiring material in the same manner as the above wiring process over thesecond wiring layer 300, a laminated wire (antireflection film 401/wire402/antireflection film 403) and a gate wire of a laminated structure(antireflection film 1/wire 2/antireflection film 3) are formed bypatterning treatment. Here for example, an Al wire of a laminatedstructure (for example TiN/Al/TiN) is formed as the laminated wire(antireflection film 401/wire 402/antireflection film 403) and the gatewire (antireflection film 1/wire 2/antireflection film 3). An interlayerinsulation film 420 (for example SiO₂) is formed over the laminated wire(antireflection film 401/wire 402/antireflection film 403) and the gatewire (antireflection film 1/wire 2/antireflection film 3) and theinterlayer insulation film 420 is removed partially and flattened by CMPas shown in FIG. 4B. As a result, the antireflection films 3 and 403(TiN) are exposed on the outermost surface.

In FIG. 4C, insulation films 64 and 65 are formed over the surface ofthe second wiring layer 300 including the antireflection films 3 and 403in sequence from the lower layer by a sputtering method, a CVD method, acoating method, or the like. The insulation film 64 comes to be a gateinsulation film 4 through a subsequent etching process and hencecomprises a material identical to the aforementioned gate insulationfilm 4. Likewise, the insulation film 65 comes to be a semiconductorlayer 5 through a subsequent etching process and hence comprises amaterial identical to the aforementioned semiconductor layer 5.

Successively, a pattern-formed hard mask insulation film 6 is formedover the insulation film 65. A silicon-contained dielectric material(for example, any one of SiN, SiO₂, and SiCOH or a laminated structureof those) is preferably used as the hard mask insulation film 6. Here,when the semiconductor layer 5 is an oxide semiconductor such asInGaZnO, InZnO, ZnO, ZnAlO, or ZnCuO for example, it is desirable tostabilize the oxidation state of the surface of the semiconductor layer5 by plasma treatment that introduces an oxidizing gas such as N₂Obefore the hard mask insulation film 6 is formed.

In FIG. 4D, a stacked structure comprising the gate insulation film 4,the semiconductor layer 5, and the hard mask insulation film 6 is formedover the antireflection film 3 functioning as a gate electrode byetching the insulation films 64 and 65 with the hard mask insulationfilm 6 used as a mask. As the etching treatment for forming the stackedstructure comprising the gate insulation film 4, the semiconductor layer5, and the hard mask insulation film 6 for example, dry etching usingany one of Cl₂, BCl₃, and N₂ or a mixed gas of those is preferably used.In the present embodiment, since the gate insulation film 4 and thesemiconductor layer 5 are formed by processing the insulation films 64and 65 by dry etching with the hard mask insulation film 6 used as themask, it is possible to microfabricate the semiconductor layer 5 whilethe semiconductor characteristics are prevented from losing.

Successively, in FIG. 4E, a via 410 coupled to the laminated wire(antireflection film 401/wire 402/antireflection film 403) and a contact9 coupled to the semiconductor layer 5 are formed. Specifically, aninterlayer insulation film 420 (for example SiO₂) is: stacked over thesurface of the interlayer insulation film 420 shown in FIG. 4D, theantireflection film 403, and the hard mask insulation film 6; andremoved partially and flattened by CMP. Successively, a via hole(contact hole) is formed at a given location (for example, over alocation coming to be a source region and a drain region in thesemiconductor layer 5 and a wire) by patterning treatment. Here, it isdesirable that the via hole (contact hole) is formed by fluorine-systemdry etching having a high selectivity to the hard mask insulation film6. Successively, a film of a barrier metal material is formed byapplying sputtering to the via hole and the contact hole and a film of avia plug material is formed by a CVD method. Successively, the surfaceis flattened by removing the barrier metal material and the via plugmaterial over the surface by CMP. By so doing, the via 410 and thecontact 9 are exposed on the surface and a third wiring layer 400 wherea bottom gate type transistor 11 is formed is formed.

A wiring layer 500 is formed over the third wiring layer 400 through anordinary Al wiring process in the same manner as the wiring layer 300.By so doing, a semiconductor device 10 shown in FIG. 2 is formed.

An example of a method for manufacturing a semiconductor device 10 shownin FIG. 3 is explained hereunder. The processes from FIG. 4A to FIG. 4Dare the same as stated earlier and thus the explanations are omitted.When a semiconductor device 10 shown in FIG. 3 is formed, a treatment ofembedding a wire is applied in succession to the process shown in FIG.4D. Specifically, an interlayer insulation film 420 (for example SiO₂)is: stacked over the surface of the interlayer insulation film 420 shownin FIG. 4D, the antireflection film 403, and the hard mask insulationfilm 6; and removed partially and flattened by CMP. Successively, a viahole (contact hole) is formed at a given location (for example, over alocation coming to be a source region and a drain region in thesemiconductor layer 5 and a wire) by patterning treatment. Here, it isdesirable that the via hole (contact hole) is formed by fluorine-systemdry etching having a high selectivity to the hard mask insulation film6. Successively, films are formed with a barrier metal material and awiring material in sequence by applying sputtering to the via hole andthe contact hole (not shown in the figure). Embedded wires 16 and 530are formed over the surface of the films formed with the wiring materialand the like by patterning of masking treatment and etching treatment.

The structures of the wiring layers 500 shown in FIGS. 2 and 3 canarbitrarily be selected in accordance with the locations (for example,whether or not an uppermost wiring layer) of the wiring layers 500, awiring width, and others.

As stated above, by a semiconductor device 10 according to the presentembodiment, since an antireflection film 3 (for example TiN) of an Alwire is used as a gate electrode, it is possible to apply Al₂O₃, SiO₂,or a gate stacked structure of Al₂O₃/SiO₂ to a wiring layer as a gateinsulation film of an active element formable in the wiring layer. Inthe case of an active element structure using a Cu wire as a back gateelectrode (bottom gate electrode) for example, by restriction on thenecessity of using a wiring cap insulation film (SiN, SiCN) as a gateinsulation film, the improvement of transistor characteristics anddevice reliability is also restricted. On the other hand, in the case ofadopting a structure according to the present embodiment, by using Al₂O₃of a high-k material having a small trap charge, SiO₂ having few Hdefects, or the like, it is possible to improve transistorcharacteristics. For example, the effects of reducing gate leakage,suppressing threshold shift, and improving threshold control, an on-offratio, and device voltage resistance can be expected.

2. Second Embodiment

A bottom gate type transistor 11 shown in First Embodiment may form alogic circuit together with another bottom gate type transistor formedin a wiring layer. For example, as shown in FIG. 5, a CMOS(Complementary Metal Oxide Semiconductor) circuit 30 can be formed witha bottom gate type transistor 11 of a P-channel type and a bottom gatetype transistor 12 of an N-channel type. The configuration of asemiconductor device 10 according to Second Embodiment of the presentinvention is explained in detail in reference to FIG. 5. In FIG. 5, asemiconductor device 10 according to Second Embodiment has an underlyinglogic element 20 formed over a substrate 100, a plurality of wiringlayers 200, 300, 400, and 500, and a CMOS circuit 30 (also called awiring layer active element) formed in the wiring layer 400.

Here, the bottom gate type transistor 11 is a P-channel type transistorand the bottom gate type transistor 12 is an N-channel type transistor.Although it is not shown in the figure, gates of the bottom gate typetransistors 11 and 12 are coupled to each other and drains of the bottomgate type transistors 11 and 12 are coupled to each other.

The structure ranging from the substrate 100 to the second wiring layer300 shown in FIG. 5 is the same as the structure shown in FIG. 2.Further, the structure of a bottom gate type transistor other than thebottom gate type transistor 12 formed in the third wiring layer 400 (forexample, the bottom gate type transistor 11) is the same as thestructure shown in FIG. 2 and hence the explanations are omitted.

In FIG. 5, the bottom gate type transistor 12 has a laminated wire(antireflection film 21/wire 22/antireflection film 23) functioning as agate wire, a gate insulation film 24, a semiconductor layer 25, a hardmask insulation film 26, and contacts 29 (barrier metals 27/contactplugs 28). The two contacts 29 couple a source region and a drain regionin the semiconductor layer 25 respectively to a wire (antireflectionfilm 501/wire 502/antireflection film 503) in the fourth wiring layer500.

The differences in configuration between the bottom gate type transistor11 and the bottom gate type transistor 12 are that the conductivity typeis different between a semiconductor layer 5 and the semiconductor layer25 and the material (structure) is different between a gate insulationfilm 4 and the gate insulation film 24. Other structures than the abovestructures are the same between the bottom gate type transistors 11 and12. Here, the gate insulation film 4 and the gate insulation film 24 maycomprise an identical material (structure).

An example of a method for manufacturing a semiconductor device 10according to Second Embodiment shown in FIG. 5 is hereunder explained inreference to FIGS. 6A to 6C.

In FIG. 6A, an underlying logic element 20, a first wiring layer 200,and a second wiring layer 300 are formed by a method (an ordinarymanufacturing process) similar to First Embodiment.

Successively, a laminated wire (antireflection film 401/wire402/antireflection film 403) and gate wires (antireflection film 1/wire2/antireflection film 3) and (antireflection film 21/wire22/antireflection film 23) of a laminated structure are formed over thesecond wiring layer 300 through a wiring process similar to FirstEmbodiment. In the example, the gate wire (antireflection film 1/wire2/antireflection film 3) and the gate wire (antireflection film 21/wire22/antireflection film 23) are coupled to each other at a location notshown in the figure. An interlayer insulation film 420 (for exampleSiO₂) is: formed over the laminated wire (antireflection film 401/wire402/antireflection film 403) and the gate wires (antireflection film1/wire 2/antireflection film 3) and (antireflection film 21/wire22/antireflection film 23); and removed partially and flattened by CMP.By so doing, the antireflection films 3, 13, and 403 (TiN) are exposedon the outermost surface. In Second Embodiment too, it is possible toform the laminated wire and the gate wires simultaneously with anidentical material through an Al wiring process similar to FirstEmbodiment. A stacked structure comprising a gate insulation film 4, asemiconductor layer 5, and a hard mask insulation film 6 is formed overthe flattened and exposed antireflection film 3 by a method similar toFirst Embodiment (refer to FIG. 4D).

In FIG. 6B, insulation films 74 and 75 are formed in sequence from thelower layer over the surfaces of the antireflection films 23 and 403,the interlayer insulation film 420, and the hard mask insulation film 6by a sputtering method, a CVD method, a coating method, or the like. Theinsulation film 74 comes to be a gate insulation film 24 through asubsequent etching process and hence comprises a material identical tothe aforementioned gate insulation film 24. Likewise, the insulationfilm 75 comes to be a semiconductor layer 25 through a subsequentetching process and hence comprises a material identical to theaforementioned semiconductor layer 25.

Successively, a pattern-formed hard mask insulation film 26 is formedover the insulation film 75. A silicon-contained dielectric material(for example, any one of SiN, SiO₂, and SiCOH or a laminated structureof those) is preferably used as the hard mask insulation film 26. Here,when the semiconductor layer 25 is an oxide semiconductor such asInGaZnO, InZnO, ZnO, ZnAlO, or ZnCuO for example, it is desirable tostabilize the oxidation state of the surface of the semiconductor layer25 by plasma treatment that introduces an oxidizing gas such as N₂Obefore the hard mask insulation film 26 is formed.

In FIG. 6C, a stacked structure comprising the gate insulation film 4,the semiconductor layer 5, and the hard mask insulation film 6 is formedover the antireflection film 3 functioning as a gate electrode of thetransistor 11 and a stacked structure comprising the gate insulationfilm 24, the semiconductor layer 25, and the hard mask insulation film26 is formed over the antireflection film 23 functioning as a gateelectrode of the transistor 12 by etching the insulation films 64, 65,74, and 75 with the hard mask insulation films 6 and 26 used as masks.As the etching treatment for forming such a stacked structure forexample, dry etching using any one of Cl₂, BCl₃, and N₂ or a mixed gasof those is preferably used. In the present embodiment, since the gateinsulation films 4 and 24 and the semiconductor layers 5 and 25 areformed by processing the insulation films 64, 65, 74, and 75 by dryetching with the hard mask insulation films 6 and 26 used as the masks,it is possible to microfabricate the semiconductor layers 5 and 25 whilethe semiconductor characteristics are prevented from losing.

Successively, in FIG. 5, a via 410 coupled to a laminated wire(antireflection film 401/wire 402/antireflection film 403), a contact 9coupled to the semiconductor layer 5, and a contact 29 coupled to thesemiconductor layer 25 are formed. Specifically, an interlayerinsulation film 420 (for example SiO2) is: stacked over the surface ofthe interlayer insulation film 420, the antireflection film 403, and thehard mask insulation films 6 and 26 shown in FIG. 6C; and removedpartially and flattened by CMP. Successively, via holes (contact holes)are formed at given locations (for example, over locations coming to besource regions and drain regions and wires in the semiconductor layers 5and 25 and wires) by patterning treatment. Here, it is desirable thatthe via holes (contact holes) are formed by fluorine-system dry etchinghaving a high selectivity to the hard mask insulation films 6 and 26.Successively, a film of a barrier metal material is formed by applyingsputtering to the via holes and the contact holes and a film of a viaplug material is formed by a CVD method. Successively, the barrier metalmaterial and the via plug material over the surface are removed by CMPand thereby the surface is flattened. By so doing, the via 410 and thecontacts 9 and 29 are exposed on the surface and a third wiring layer400 in which the bottom gate type transistors 11 and 12 are formed isformed. A laminated wire is formed over the contacts 9 and 29 through awiring process similar to First Embodiment over the third wiring layer400. In the present example, a wire over the contact 9 coupled to thedrain region in the semiconductor layer 5 and a wire over the contact 29coupled to the drain region in the semiconductor layer 25 are coupled toeach other at a location not shown in the figure.

As stated above, in a semiconductor device 10 according to the presentembodiment, it is possible to form a logic circuit (for example, a CMOScircuit 30) having a plurality of bottom gate type transistors 11 and 12formed simultaneously in an identical wiring layer.

A semiconductor device 10 according to the present embodiment also usesantireflection films 3 and 23 (for example TiN) for an Al wire as gateelectrodes in the same manner as First Embodiment and hence theselectivity of a gate insulation film of a logic circuit capable ofbeing formed in a wiring layer improves. As a result, in a semiconductordevice 10 according to the present embodiment, the effects of improvingtransistor characteristics in a logic circuit, such as the effects ofreducing gate leakage, suppressing threshold shift, and improvingthreshold control, an on-off ratio, and device voltage resistance, canbe expected.

Although the configuration of forming two bottom gate type transistors11 and 12 in an identical wiring layer is shown in the example shown inFIG. 5 here, the present invention is not limited to the configurationand it is also possible to form a plurality of bottom gate typetransistors in another wiring layer. Further, although explanations aremade by using a CMOS circuit as the example in the present embodiment,it goes without saying that the present invention can be applied toanother logic circuit (for example, a transfer gate, a logical operationcircuit such as an AND circuit, an NAND circuit, an OR circuit, or anNOR circuit, or a memory cell such as an SRAM or a DRAM) as long as abottom gate type transistor formed in a wiring layer can be used.

An example of the planar structure of a bottom gate type transistor 11according to the present embodiment is hereunder explained in referenceto FIGS. 7 and 8. FIG. 7 is a view showing the planar structure of abottom gate type transistor 11 according to an embodiment. FIG. 8 is aview showing the cross-sectional structure of the bottom gate typetransistor 11 taken on line A-A′ in FIG. 7.

The example of the planar structure shown in FIG. 7 shows a pectinategate structure and it can be driven effectively at a large current evenin a small area. Hereinafter, a gate wire (antireflection film 1/wire2/antireflection film 3) of the bottom gate type transistor 11 isreferred to as a gate wire 41, a contact 9 coupled to a source region ofa semiconductor layer 5 is referred to as a source contact 42, and acontact 9 coupled to a drain region of the semiconductor layer 5 isreferred to as a drain contact 43. Further, an upper layer wire coupledto the source contact 42 is referred to as a source wire 44 and an upperlayer wire coupled to the drain contact 43 is referred to as a drainwire 45.

In FIGS. 7 and 8, the drain wire 45 shows a pectinate shape and has aplurality of wires (hereunder referred to as drain pectinate wires)extending from one wire in the direction perpendicular to the wire. Thesource wire 44 is formed between the plural drain pectinate wires in aplanar view and extends in parallel with the pectinate wires. The gatewire 41 shows a pectinate shape and has a plurality of wires (hereunderreferred to as gate pectinate wires) extending from one wire in thedirection perpendicular to the wire. The gate pectinate wires are formedbetween the drain pectinate wires and the source wire 44 in a planarview and extend in parallel with the drain pectinate wires and thesource wire 44.

A plurality of source contacts 42 are formed so as to couple the sourcewire 44 to the semiconductor layer 5 and a plurality of drain contacts43 are formed so as to couple the drain pectinate wires in the drainwire 45 to the semiconductor layer 5.

By the above configuration, it is possible to: densely form the gatewire, the source contacts 42, and the drain contacts of the bottom gatetype transistor 11; and effectively increase on-site current per area.By so doing, it is possible to materialize area reduction and a highon-site current and obtain a downsized high-performance wiring switch.

FIG. 9 is a view showing an example of the structure(high-voltage-resistant structure) of a bottom gate type transistoraccording to an embodiment. In FIG. 9, it is possible to increase devicevoltage resistance by separating a gate wire 41 from a drain contact 43at a given distance, namely by adopting an offset structure between agate and a drain.

An aforementioned wiring layer active element (for example, a bottomgate type transistor 11 or a CMOS circuit 30) is preferably coupledelectrically to an underlying logic circuit including an underlyinglogic element 20. For example, a wiring layer active element (forexample, a bottom gate type transistor 11 or a CMOS circuit 30) can beused as an I/O (Input/Output) signal switch or a power switch by beingformed in a lower wiring layer of a signal pad or a power pad. FIG. 10shows an example of using a wiring layer active element 11 as an outputsignal switch, FIG. 11 shows an example using a wiring layer activeelement 11 as an input signal switch, and FIG. 12 shows an example ofusing a wiring layer active element as a power switch.

FIG. 10 is a view showing an example of the relation of connectionbetween a wiring layer active element and an underlying logic circuitaccording to an embodiment. Here, a circuit comprising an underlyinglogic element 20 is referred to as an underlying logic circuit 600 and acircuit having a wiring layer active element 11 is referred to as awiring layer circuit 700. A wiring layer active element 11 is formed ina wiring layer and hence a power-supply voltage VDD1 (for example 12V)different from a power-supply voltage VDD2 (for example 3V) supplied tothe underlying logic circuit 600 can be supplied. The underlying logiccircuit 600 in the present example operates in response to thepower-supply voltage VDD2 supplied from a second power source and has anNAND circuit and a clock tree circuit including a plurality of invertercircuits. An output signal of the underlying logic circuit 600 isinputted into a gate wire 41 of the wiring layer active element 11. Asource wire 44 of the wiring layer active element 11 is coupled to afirst power source (power-supply voltage VDD1) and an output signal wireOUT and a drain wire 45 is coupled to a third power source (for exampleGND).

By such a configuration, the wiring layer circuit 700 operates as anoutput signal switch to control the transmission of a signal from theunderlying logic circuit 600 to the output signal wire OUT. The wiringlayer circuit 700 is formed in a wiring layer over the underlying logiccircuit 600 and hence it is possible to consolidate the underlying logiccircuit 600 operating at a low power-supply voltage VDD2 and the wiringlayer active element 11 operating at a high power-supply voltage VDD1 inan identical chip. By a semiconductor device 10 according to the presentembodiment therefore, it is possible to materialize a circuitconfiguration to control the output of an underlying logic circuit 600of a low operating voltage with a wiring layer circuit 700 of a highoperating voltage while a chip area is prevented from increasing.Further, a wiring layer circuit 700 is formed in a wiring layer over anunderlying logic circuit 600 and hence it is possible to change thedisposition of an output signal switch to control an output signalcoming from the underlying logic circuit 600 and the access point of theoutput signal by changing the layout of the wiring layer withoutchanging the layout of the underlying logic circuit 600. By so doing, itis possible to avoid a turn-back process related to the modification ofthe underlying logic circuit 600 and reduce design time significantly.

FIG. 11 is a view showing another example of the relation of connectionbetween a wiring layer active element and an underlying logic circuitaccording to an embodiment. Here, a circuit comprising an underlyinglogic element 20 is referred to as an underlying logic circuit 601 and acircuit having wiring layer active elements 11 and 12 is referred to asa wiring layer circuit 701. The wiring layer active elements 11 and 12are formed in a wiring layer and hence a power-supply voltage VDD1 (forexample 12V) different from a power-supply voltage VDD2 (for example 3V)supplied to the underlying logic circuit 601 can be supplied. Theunderlying logic circuit 601 in the present example has an invertercircuit operating in response to the power-supply voltage VDD2 suppliedfrom a second power source. The wiring layer circuit 701 has a pluralityof signal control circuits each of which includes the wiring layeractive element 11 in which a source is coupled to a first power source(power-supply voltage VDD1) and a gate is coupled to an input signalwire and the wiring layer active element 12 in which a source is coupledto a third power source (GND) and a gate is coupled to an output signalwire. Here, drains of the wiring layer active elements 11 and 12 and agate of the wiring layer active element 12 are coupled to an outputsignal wire (an input signal wire of the next stage). An output signalwire VOUT in a signal control circuit at the final stage of the wiringlayer circuit 701 is coupled to an input terminal of the invertercircuit in the underlying logic circuit 601.

By such a configuration, the wiring layer circuit 701 operates as aninput signal switch to control the transmission of an input signal(voltage Vin) to the underlying logic circuit 601. In the same way asdescribed above, the wiring layer circuit 701 is formed in a wiringlayer over the underlying logic circuit 601 and hence it is possible toconsolidate the underlying logic circuit 601 operating at a lowpower-supply voltage VDD2 and the wiring layer active element 11operating at a high power-supply voltage VDD1 in an identical chip. By asemiconductor device 10 according to the present embodiment therefore,it is possible to materialize a circuit configuration to control aninput into an underlying logic circuit 601 of a low operating voltagewith a wiring layer circuit 701 of a high operating voltage while a chiparea is prevented from increasing. Further, a wiring layer circuit 701is formed in a wiring layer over an underlying logic circuit 601 andhence it is possible to change the disposition of an input signal switchto control an input signal to the underlying logic circuit 601 and theaccess point of the input signal by changing the layout of the wiringlayer without changing the layout of the underlying logic circuit 601.By so doing, it is possible to avoid a turn-back process related to themodification of the underlying logic circuit 601 and reduce design timesignificantly.

FIG. 12 is a view showing still another example of the relation ofconnection between a wiring layer active element and an underlying logiccircuit according to an embodiment. Here, a circuit comprising anunderlying logic element 20 is referred to as an underlying logiccircuit 602 and a circuit having a wiring layer active element 11 isreferred to as a wiring layer circuit 702. The underlying logic circuit602 according to the present example has an inverter circuit operatingin response to a power-supply voltage VDD2 supplied from a second powersource through the wiring layer circuit 702. Specifically, the wiringlayer circuit 702 has a P-channel type bottom gate type transistor 11 inwhich a source is coupled to the second power source (power-supplyvoltage VDD2) and a drain is coupled to a power wire of the underlyinglogic circuit 602. The underlying logic circuit 602 has an invertercircuit comprising a P-channel type transistor in which a source iscoupled to the drain of the bottom gate type transistor 11 and anN-channel type transistor in which a source is coupled to a third powersource (GND).

By such a configuration, the wiring layer circuit 702 controlsconnection between the second power source (power-supply voltage VDD2)and the underlying logic circuit 602 in response to a voltage Vininputted into a gate of the wiring layer active element 11. That is, thewiring layer circuit 702 functions as a power switch to control thesupply of the power-supply voltage VDD2 to the underlying logic circuit602. The wiring layer circuit 702 is formed in a wiring layer over theunderlying logic circuit 602 and hence it is possible to change thedisposition of the power switch to control power supply to theunderlying logic circuit 602 and the supply destination of electricpower by changing the layout of the wiring layer without changing thelayout of the underlying logic circuit 602. By so doing, it is possibleto avoid a turn-back process related to the modification of theunderlying logic circuit 602 and reduce design time significantly.

The wiring layer circuits 700, 701, and 702 are not limited to theaforementioned circuit configurations as long as they are circuitsincluding the wiring layer active elements (bottom gate type transistors11 and 12 and CMOS circuits 30) shown in the present embodiments.Further, the underlying logic circuits 600, 601, and 602 are not limitedto the aforementioned circuit configurations as long as they haveunderlying logic elements 20 controlled by the wiring layer circuits700, 701, and 702.

As stated above, by a semiconductor device 10 according to the aboveembodiments, it is possible to arbitrarily select the type of a gateinsulation film by using an antireflection film (cap film) formedthrough an Al wiring process as a gate wire. As a result, it is possibleto improve process margin related to the improvement of characteristics.

Although embodiments according to the present invention have heretoforebeen described in detail, a concrete configuration is not limited to theembodiments and any modification is included in the present invention aslong as the modification is in a range not deviating from the tenor ofthe present invention. First Embodiment and Second Embodiment can beincorporated with each other in a technologically possible range.Further, it is also possible to form wiring layer active elements 11,12, and 30 through an Al wiring process and form another wiring layerand an underlying logic element 20 through a Cu wiring process and thusform a semiconductor device.

FIG. 13 is a view showing an example of the configuration of asemiconductor device 10 consolidating a wiring layer formed through anAl wiring process and a wiring layer formed through a Cu wiring process.In FIG. 13, a semiconductor device 10 of the present example has anunderlying logic element 20 formed over a substrate 100, a plurality ofwiring layers 250, 350, 400, and 500, and a bottom gate type transistor11 (also called a wiring layer active element) formed in the wiringlayer 400.

The first wiring layer 250 and the second wiring layer 350 over thesubstrate 100 are formed through a Cu wiring process, the configurationsof the underlying logic element 20, the third wiring layer 400 includingthe bottom gate type transistor 11, and the fourth wiring layer 500formed thereover are similar to the configuration shown in FIG. 3, andhence the explanations are omitted.

The first wiring layer 250 is formed over the underlying logic element20. The underlying logic element 20 is coupled to another element, apower source, and the like through the first wiring layer 250. Forexample, the first wiring layer 250 has an embedded wire 230 to couplethe underlying logic element 20 to the second wiring layer 350. Theembedded wire 230 includes a barrier metal 231 (for example TiN) and awire 232 containing Cu as the main component. The embedded wire 230comprises a contact section embedded into an interlayer insulation film221 formed over the underlying logic element 20 and a wiring sectionembedded into an interlayer insulation film 222 formed thereover. Adiffusion prevention film 251 such as an SiCN film is formed over theembedded wire 230 and the interlayer insulation film 222.

The second wiring layer 350 has embedded wires 330 and 333 to couple thefirst wiring layer 250 to the third wiring layer 400. The embedded wire330 includes a barrier metal 331 (for example TiN) and a wire 332containing Cu as the main component. The embedded wire 330 is embeddedinto an interlayer insulation film 321 formed over the diffusionprevention film 251 and the diffusion prevention film 251 and comprisesa contact section coupled to the embedded wire 230 and a wiring sectionembedded into an interlayer insulation film 322 thereover. A diffusionprevention film 351 such as an SiCN film is formed over the embeddedwire 330 and the interlayer insulation film 322. The embedded wire 333includes a barrier metal 334 (for example TiN) and a wire 335 containingCu as the main component. The embedded wire 333 is embedded into aninterlayer insulation film 323 formed over the diffusion prevention film351 and the diffusion prevention film 351 and has a contact sectioncoupled to the embedded wire 330.

The configurations of the third wiring layer 400 and the fourth wiringlayer 500 are similar to FIG. 3 but an Al wire (antireflection film401/wire 402/antireflection film 403) and a gate wire (antireflectionfilm 1/wire 2/antireflection film 3) formed through an Al wiring processare formed over the embedded wire 333 so as to be coupled to theembedded wire 333.

The wiring layer 500 may either be materialized with an embedded wire 16in the same manner as FIG. 3 or have a wiring structure similar to FIG.2.

What is claimed is:
 1. A method for manufacturing a semiconductor deviceincluding the steps of: forming an underlying logic element over asubstrate; forming an aluminum wire in a wiring layer over theunderlying logic element; forming an antireflection film over thealuminum wire; forming a gate insulation film and an oxide semiconductorlayer in sequence from the lower layer over the antireflection film, andforming a source contact and a drain contact coupled to the oxidesemiconductor layer.
 2. A method for manufacturing a semiconductordevice according to claim 1, wherein the step of forming an aluminumwire includes a step of forming a first aluminum wire and a secondaluminum wire in an identical process; the step of forming anantireflection film includes a step of forming a first antireflectionfilm over the first aluminum wire and a second antireflection film overthe second aluminum wire in an identical process; the step of forming agate insulation film and an oxide semiconductor layer includes steps offorming a first gate insulation film, a first oxide semiconductor layer,and a first hard mask in sequence from the lower layer over the firstantireflection film, forming an insulation film for a second gateinsulation film, an oxide semiconductor layer for a second oxidesemiconductor layer, and a second hard mask in sequence from the lowerlayer over the first hard mask and the second antireflection film, andforming the second gate insulation film and the second oxidesemiconductor layer over the second antireflection film by etching; thestep of forming a source contact and a drain contact includes a step offorming a first source contact and a first drain contact coupled to thefirst oxide semiconductor layer and a second source contact and a seconddrain contact coupled to the second oxide semiconductor layer in anidentical process, and the conductivity type of the first oxidesemiconductor layer is different from the conductivity type of thesecond oxide semiconductor layer.
 3. A method for manufacturing asemiconductor device according to claim 2, wherein the first aluminumwire is coupled to the second aluminum wire, and the first drain contactis coupled to the second drain contact through a wire.